1. Field of the Invention
The present invention relates to integrated circuit design, and more particularly to a lock detection circuit and method for a phase locked loop (PLL) system.
2. Description of the Prior Art
FIG. 1 shows a block diagram of a typical phase locked loop system in accordance with prior art. The phase locked loop system 100 includes a pre-divider 110, a phase frequency detector (PFD) 120, a charge pump 130, a low pass filter (LPF) 140, a voltage controlled oscillator (VCO) 150, a post-divider 160, and a feedback divider 170. The pre-divider 110 receives an input clock signal PIN and outputs a divided reference clock signal RCLK to the phase frequency detector 120. The phase frequency detector 120 is connected to the feedback divider 170 and receives a divided VCO clock signal VCLK therefrom. The phase frequency detector 120 has two output terminals outputting an UP clock signal and a DOWN clock signal to the charge pump 130. The charge pump 130 is connected to the low pass filter 140 and the voltage controlled oscillator 150. The voltage controlled oscillator 150 is connected to the post-divider 160 and outputs a voltage controlled oscillating clock signal VCO_CLOCK. The output terminal of the post-divider 160 provides the output clock signal POUT of the phase locked loop system 100 and connects to the feedback divider 170. The feedback divider 170 divides the output clock signal POUT and outputs the divided VCO clock signal VCLK to the phase frequency detector 120.
When the phase locked loop system 100 is in steady state, the phase difference and frequency difference between the reference clock signal RCLK and the divided VCO clock signal VCLK received by the phase frequency detector 120 should approach zero. In such a state, the phase locked loop is said to be in a “lock” condition or “locked”. After initialization, a phase locked loop needs a period of delayed time before it attains a steady state. The output clock signal POUT of the phase locked loop system 100 before it acquires lock is not stable and should not be used. Accordingly, a lock detection circuit is usually employed for a phase locked loop system to determine if the phase locked loop system is already in a locked state. Such a lock detection circuit avoids the frequency measuring overhead for the output clock signal of a phase locked loop system so as to simplify any testing routine.
FIG. 2A shows a schematic diagram of a conventional lock detection circuit 200 which includes an exclusive OR (XOR) gate 210 and a one-shoot counter 220. The XOR gate 210 receives the UP clock signal and the DOWN clock signal of the phase locked loop system 100, and then outputs a phase error signal PHERR to the reset terminal TRESET of the one-shoot counter 220. On the other hand, the reference clock signal RCLK of the phase locked loop system 100 is coupled to the clock input terminal TCLK of the one-shoot counter 220. The output terminal of the one-shoot counter 220 provides a phase lock indicating signal LOCK. When a locked state is detected, the phase lock indicating signal LOCK goes high and remains at high level until before a reset signal is received at the reset terminal TRESET. The lock detection circuit 200 is capable of detecting the static phase error of a phase locked loop system. The phase difference at the input of the phase frequency detector 120 is called the static phase error. In ideal case, the static phase error is zero when the phase locked loop system is locked. In practice, however, a phase locked loop system will be considered to be locked as long as the static phase error is less than a predetermined threshold.
As shown in FIG. 2A, the XOR'ed result PHERR of the UP clock signal and the DOWN clock signal may represent the static phase error. After the phase locked loop system starts running, the clock input terminal TCLK of the one-shoot counter 220 keeps receiving the reference clock signal RCLK. If there is no valid PHERR resets the one-shoot counter 220 within a predetermined number of RCLK clocks, the one-shoot counter 220 will output a high level and remain at the high level until any valid PHERR is received at the reset terminal TRESET.
As described above, the lock detection circuit 200 determines the level of the static phase error according to the XOR result of the UP clock signal and the DOWN clock signal from the phase locked loop system 100. Several signal diagrams corresponding to different levels of static phase errors are shown in FIG. 2B through FIG. 2D. All diagrams contain the relative waveforms of the UP clock signal, the DOWN clock signal, and the result phase error signal PHERR. In ideal case, when the phase locked loop system 100 is perfectly locked, the UP clock signal and the DOWN clock signal will have identical frequency and phase such that the phase error will remain at low level as shown in FIG. 2B. In practical case, the frequencies or phases of the UP clock signal and the DOWN clock signal will be different as shown in FIG. 2C. The difference therebetween is transformed to a high level through the XOR gate 210. The duration of the high level represents the level of the phase error. When the frequency and phase difference between the UP clock signal and the DOWN clock signal is minor as shown in FIG. 2D, the phase locked loop system may be considered to be locked in this case. A practical lock detection circuit should be able to detect the unlocked situation as shown in FIG. 2C and neglect the noise as shown in FIG. 2D.
Due to element mismatching, process variation, and temperature, the conventional lock detection circuit 200 sometimes fails to disregard a negligible minor static phase error such that an already locked phase locked loop may be misconstrued to be unlocked. In other words, the phase error tolerance of the conventional lock detection circuit 200 may fail to meet a practical requirement. In addition, the phase error tolerance of the conventional lock detection circuit 200 of FIG. 2A can not be changed. It lacks the capability and flexibility to adjust the phase error tolerance for different applications. In view of the drawbacks of the conventional lock detection circuit, there is a need to provide a more flexible lock detection circuit which is also invariant with respect to element mismatching, process variation, or temperature.